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 MX23L6412
SEQUENTIAL 64M-BIT MASK ROM
FEATURES
* Bit organization - 4M x 16 (word mode only) - 256 words/page - Total 16K pages * Sequential access at 200ns cycle time in a page * Asynchronous chip enable input (ALEH, ALEL) * Access time - Read latency time: 950ns - Read cycle time: 200ns - RD access time: 150ns * Current - Operating:25mA(max.) - Address input:2mA(max.) - Standby:20uA(max.) * Supply voltage - 3.0V~3.6V * Package - 32 pin TSOP
ORDER INFORMATION
Part No. MX23L6412TC-20 Read Cycle Time 200ns Package 32 pin TSOP
GENERAL DESCRIPTION
The product is a 64M bits (4M x 16) mask ROM composed of 16K pages, and each consists of 256 words memory cell array. This mask ROM has a 16 bit address input / data output bus (AD0~AD15), two address latch enable pins (high : ALEH, low : ALEL), a read strobe (RD). There are 3 modes, Stand-by mode, Active mode, and Address input mode. Stand-by mode is a non-operating state, and has the smallest current dissipation. Active mode is an operating state, and data output is possible. Address input mode is a state of address input. Address input is through AD bus when ALEL is high. The high and low 16 bit addresses are latched at ALEH'sand ALEL falling edges. As for high 16 bit address, A0~A6 are through 7 bit address register, A7~A15 are not used internally. As for low 16 bit address, A1~A8 are through 8 bit address counter, A9~A15 are through 7 bit address register, and A0 are not used internally. High address input must be done before low address input, and both address inputs are needed for page change or address change in a same page. After address inputs, CE goes high at ALEH falling edge and RD doesn't toggle, the ROM is in stand-by mode. After ROM turned into Active mode from Address input mode, it takes tL time to read. In a page, sequential read access is possible at tCYC cycle time. Sequential read operation (increment of internal address counter) is done at every falling edge of RD. At the end of a page, internal address counter raps around to the beginning of the page.
P/N:PM0652
REV. 1.5, MAR. 11, 2003
1
MX23L6412
PIN CONFIGURATION
32 TSOP
NC CE VSS AD12 AD13 AD14 AD15 NC NC AD0 AD1 AD2 AD3 VCC ALEL NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC RD VCC AD11 AD10 AD9 AD8 NC NC AD7 AD6 AD5 AD4 VSS ALEH NC
PIN DESCRIPTION
Symbol AD0~AD15 ALEH ALEL CE RD VCC VSS NC Pin Function Address Input / Data Output Address Latch Enable High Address Latch Enable Low Chip Enable Input Read Strobe Input Power Supply Pin Ground Pin No Connection
MX23L6412
TRUTH TABLE
Mode Address Input Address Input Active Active Stand-by Operation High address input Low address input Internally active Data read Stand-by * CE L X X X X ALEH H L L L H-->L ALEL H H L L L RD X X H L X AD Bus Address input Address input Floating Data output Floating
Note: Please see "standby mode" timing diagram.
BLOCK DIAGRAM
RD ALEH ALEL Enable CE CE Reg.
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
Input Buffer
Row Decoder
Address Register
Memory Cell Array 256 words/ Page
Output Buffer
Address Register
Column Decoder Address Presettable Counter Enable Clock
Latch x 16
P/N:PM0652
REV. 1.5, MAR. 11, 2003
2
MX23L6412
ABSOLUTE MAXIMUM RATINGS
Item Voltage on any Pin Relative to VSS Ambient Operating Temperature Storage Temperature Symbol VIN Topr Tstg Ratings -0.5V to 4.6V 0 C to 70 C -55 C to 125 C
DC CHARACTERISTICS (Ta = 0 C~70 C, VCC = 3.3V10%)
Item Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Operating Current Address Input Current Standby Current (CMOS) Input Capacitance Output Capacitance Symbol VOH VOL VIH VIL ILI ILO ICC1 ICC2 ISTB CIN COUT MIN. 2.0V 2.0V -0.5V -10uA -10uA MAX. 0.4V VCC+0.5V 0.8V 10uA 10uA 25mA 2mA 20uA 12pF 12pF Conditions IOH = -0.4mA IOL = 2mA
VIN = 0V to 3.6V VOUT = 0V to 3.6V Cycle = 200ns, VIN = VIH or VIL, active mode Cycle = 100ns, VIN = VIH or VIL, address input mode Cycle = 200ns, VIN = VCC0.3V or 0V0.3V,stand-by mode Ta = 25 C, f = 5MHz, VIN = 0V Ta = 25 C, f = 5MHz, VOUT = 0V
AC CHARACTERISTICS (Ta = 0 C~70 C, VCC = 3.3V10%)
Item ALEL Setup Time ALE Delay Time Address Setup Time Address Hold Time Read Latency Time Read Cycle Time CE Setup Time CE Hold Time RD Access Time RD High Time Output Hold Time Output Float Time Release Time Symbol tALES tALED tAS tAH tL tCYC tCES tCEH tRD tRDH tOH tDF tR MIN. 70ns 70ns 30ns 0 950ns 200ns 50ns 0ns 50ns 0 40ns 0 MAX. Conditions
150ns
P/N:PM0652
REV. 1.5, MAR. 11, 2003
3
MX23L6412
TIMING DIAGRAM Address Input Mode and Active Mode
Address Input Mode Active Mode
ALEH
tALES tALED tL
ALEL
tCYC tCES
CE
tCEH tR
tRDH
RD
tAS tAH
tRD AL D0
tOH D1 AH
AD[0:15]
AH
DN
tDF
Standby Mode
Active Mode CE Latch tALED Standby Mode
(1)
ALEL
tALES
ALEH
tCEH
CE
tCES
(2)
ALEL
(Low)
Active Mode
CE Latch
Standby Mode
tALES
ALEH
CE
P/N:PM0652
REV. 1.5, MAR. 11, 2003
4
MX23L6412
AC Test Conditions
2.4V
2.4V
INPUT
0.4V
TEST POINTS
0.4V
2.0V
2.0V
OUTPUT
0.8V
TEST POINTS
0.8V
* Input Rise and Fall Times : <10ns * Output Load : 1TTL+100pF (without active current loading)
P/N:PM0652
REV. 1.5, MAR. 11, 2003
5
MX23L6412
PACKAGE INFORMATION
P/N:PM0652
REV. 1.5, MAR. 11, 2003
6
MX23L6412
REVISION HISTORY
REVISION 1.1 1.2 1.3 1.4 1.5 DESCRIPTION To revise the CE setup time tCES as 50ns(min.) instead of 30ns Modify Access time--Read latency time:1000ns--->950 Add Package Information Change Standby Current:500uA(max.)--->20uA(max.) Add Standby Mode Timing Diagram To modify Package Information PAGE P3 P1,3 P5 P1,3 P2,4 P6 DATE JUL/26/1999 OCT/13/2000 AUG/17/2001 FEB/20/2002 MAR/11/2003
P/N:PM0652
REV. 1.5, MAR. 11, 2003
7
MX23L6412
MACRONIX INTERNATIONAL CO., LTD.
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MACRONIX AMERICA, INC.
TEL:+1-408-262-8887 FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


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